library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity maindec is
    port(
    Op: in std_logic_vector(5 downto 0);
    MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump: out std_logic;
    AluOp: out std_logic_vector(1 downto 0)
    );
end maindec;

architecture behav of maindec is
    signal result: std_logic_vector(8 downto 0);
begin
    result <=
        "000011010"
            when Op = "000000" else
        "100101000"
            when Op = "100011" else
        "010100000"
            when Op = "101011" else
        "001000001"
            when Op = "000100" else
        "000101000"
            when Op = "001000" else
        "000000100"
            when Op = "000010" else
        (others => '-');

    MemToReg <= result(8);
    MemWrite <= result(7);
    Branch <= result(6);
    AluSrc <= result(5);
    RegDst <= result(4);
    RegWrite <= result(3);
    Jump <= result(2);
    AluOp <= result(1 downto 0);
end behav;